The past several years have witnessed a dramatic increase in the capabilities of high-speed, high-density, broadband data communication systems. Pertinent such systems range anywhere from broadcast or cablecast HDTV systems, local area and wide area (LAN, WAN) systems for multimedia, fibre to the home (FTTH) applications and board-to-board interconnections in exchange systems and computers.
In any one of the foregoing applications, it should be noted that bidirectional data communication is in digital form and, accordingly, clock and data recovery circuitry is a key component of the efficient functioning of modern data communications systems. The ability to regenerate binary data is an inherent advantage of transmitting information digitally as opposed to transmitting such information in analog form. However, in order for the intelligence signal to be correctly reconstructed at the receiving end, the transmitted binary data must be regenerated with the fewest possible number of bit errors, requiring received data to be sampled at an optimum sample rate and at an optimum instance of time. Given the bandwidth constraints imposed on most modern data communication systems, it is generally impractical to transmit the requisite sampling clock signal separate from the transmitted datastream. Timing information is consequently derived from the incoming transmitted data signal itself. Extraction of the implicit timing signal is generally termed timing recovery (or clock recovery) in it's functional role in general digital receiver technology, is traditionally performed by a phase-lock-loop system such as that illustrated in FIG. 1.
Phase-lock-loops operate to compare the frequency and/or phase of an incoming serial datastream to a periodic reference clock signal generated by an oscillator circuit, and to adjust the operational frequency and phase characteristics of the oscillator until its output stream is “locked” in both frequency and phase to the data signal. A reference clock is thereby established which, in turn, controls operation of a decision circuit which regenerates (or retimes) the data signal. The phase-lock-loop suitably comprises a phase detector 10 whose output is coupled to a charge pump circuit 12, operatively connected, in turn, to a loop filter 13 and a voltage controlled oscillator (or VCO) 14.
The data signal is received at a data input of the phase detector 10, in which the occurrence of the data's rising edge (its phase) is compared in time to the occurrence of a rising edge (the phase) of an output signal of the VCO 14. Conventionally, the phase detector incorporates logic circuitry (in effect a logical XNOR function) which precludes an output signal from being issued during phase comparisons unless two rising edges are present during a comparison cycle. This feature prevents the phase-lock-loop from becoming unstable by trying to perform a phase comparison between a VCO rising edge and a DATA ZERO bit (necessarily without a rising edge). It will be understood that the phase comparison result in such a situation would indicate either an infinite phase lead or an infinite phase lag, thus causing the VCO frequency to run out of control.
According to convention, the phase detector 10 issues a PUMP UP signal 16 to the charge pump 12 if the datastream phase leads the VCO signal, and issues a PUMP DN 18 if the datastream phase lags the VCO signal. PUMP UP and PUMP DN are directed to the charge pump 12 which sources or sinks a particular amount of current (the pump current) to or from, respectively, the loop filter 13. Voltage is developed as the pump current is sourced or sunk, with the voltage being used to control the operational frequency of the VCO 14. The sign of the VCO control voltage variation depends on whether the phase of the datastream leads or lags the phase of the VCO output and its magnitude is a function of the extent of the phase lead or phase lag. Thus, the operational frequency of the VCO 14 is increased or decreased, as appropriate, to reduce the phase lead or phase lag of the inputs to the phase detector 10. The phase-lock-loop thus ensures that the VCO output, which is used as a timing reference, is locked in phase with the incoming serial datastream. Once the PLL is “locked”, the timing reference signal (i.e., the VCO output) is used to control operation of a decision circuit 19 which defines regenerated or retimed data which defines regenerated or retimed data.
A particular shortcoming of prior art phase-lock-loop systems is that the charge pump is required to source and sink current which precisely represents the magnitude and polarity of a phase difference between incoming data and the VCO. In addition, for a type II or a type IV phase detector operating in quasi flywheel mode, the charge pump is required to source and sink current in such a manner that the output current, averaged over a correction cycle, equals 0. In other words, the charge pump should ideally only cause corrections to be made to the operating characteristics of the VCO which result from consistent frequency shifts of the datastream, such that the VCO is locked to the mean phase of the incoming datastream rather than to the phase of any specific data bit.
Maintaining perfect phase-lock VCO to data, however, is particularly difficult for conventional prior art-type phase-lock-loop circuits operating in the GHz range, because of the internal construction of conventional prior art-type charge pump circuits. In addition, the source and sink current waveforms, of such conventional charge pump circuits, exhibit significant amounts of offset and “glitch errors” which cause the source and sink current waveforms to be non-symmetrical. This non-symmetry necessarily results in a residual charge being left on the filter capacitor at the end of a correction cycle and further causes a non-zero increment to the control voltage Vc to the VCO. The terms “offset” and “glitch errors” refer to fluctuations in the source and/or sink current waveforms and represent quantifiable departures from a smooth waveform characteristic. These fluctuations are caused by a variety of factors, the majority of which are functions of the physical and electrical properties of semiconductor integrated circuit transistors and integrated circuit charge pumps manufactured therefrom and exhibit the response characteristics illustrated in FIG. 2.
Offset is an undesirable quantum of charge output from a charge pump when the PUMP UP and PUMP DN signals applied to the input of the charge pump are identical (i.e., the output of the charge pump should be flat or zero). This DC offset current tends to perturb the system in one direction or the other and results in timing jitter at the output of the VCO. Glitch energy is a sharp transition peak signal defined at the output of the charge pump, caused in major part by transition edge (clock) feed through effects of the input signals.
To better understand the causes of offset and glitch errors, it will be helpful to review the common and well-known charge pump architecture depicted in simplified form in FIG. 3.
Conceptually, a charge pump may be viewed as a “pump up” current source 20 connected in series with a switch 22 to provide an output source current in response to a PUMP UP signal issued by a, for example, phase detector. Similarly, a “pump down” current sink 24 is coupled between a Vss supply and a second switch 26 which, together function to define a sink current in response to a PUMP DN signal from the phase detector. While relatively simple, the simplified charge pump design of FIG. 3 can be used to illustrate several practical problems with contemporary charge pump design. For example, DC mismatches in the up and down current sources 20 and 24 necessarily cause a DC offset in the charge pump output when both PUMP UP and PUMP DN activate the respective switches 22 and 26, at the same time.
Likewise, the voltage node between the current source 20 and switch 22 on the “UP” side of the charge pump will rise to VDD when the pump-up switch 22 is in an open condition. The voltage node between the current sink 24 and switch 26 on the pump-down side of the charge pump will go to Vss when the pump-down switch is in an open condition. These conditions cause a DC offset in the charge pump output that is necessarily dependent on the output voltage because of well-known parasitic capacitance effects that are present on the above-described nodes. In addition to the offset effects inherent in contemporary charge pump designs, it will be understood that as the switches 22 and 26 open and close in response to PUMP UP and PUMP DN signals issued by the phase detector, voltage spikes, ground bounce, and the like, will cause a sharp “ring” spike at transition edge instants. Spikes, ringing and other non-linearities introduced by switch transients, clock feed through effects, and the like, are subsumed into the term “glitch energy”.
Accordingly, prior art-type charge pump circuits do not provide a smooth, constant and symmetrical response characteristic between their source and sink currents during phase lock, thus introducing variation to the loop filter and, consequently the VCO output. This variability becomes proportionately more significant as the VCO frequency increases. Accordingly, for high-speed phase-lock-loops, there is a demonstrated need for a high precision charge pump which is designed and constructed such that glitch errors and DC offsets are minimized for both source and sink phases of a detection cycle, such that the average current, integrated across the cycle, more closely approximates zero.